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Archive for the ‘6.ISSUES’ Category

Gate Oxide Breakdown

April 23, 2013 Leave a comment

Outline

  • Motivation
  • Background
  • Root Causes for Gate Oxide Breakdown
  • Symptoms of Gate Oxide Breakdown
  • Failure Models
  • Prediction of Gate Oxide Breakdown
  • Protection Against Gate Oxide Breakdown Conclusion

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Categories: 6.ISSUES

Power Supply Effects on Noise Performance

April 11, 2013 Leave a comment

Executive Summary

PSRR is an often misunderstood and little used specification. Understanding the PSRR (Power Supply Rejection Ratio) of analog circuits is an important step toward improving overall mixed-signal system performance. The fact is that the PSRR of analog circuits, including ADCs (Analog-to-Digital Convert- ers), DACs (Digital-to-Analog Converters) and op amps, is usually much worse at high frequencies than the DC PSRR generally seen on data sheets. However, most manufacturers have historically only specified DC PSRR. While this applica- tion note concerns itself with Analog-to-Digital Converters, it applies equally as well to Digital-to-Analog Converters, am- plifiers and to circuits in general, integrated or otherwise.

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Categories: 6.ISSUES

Antenna Effect

June 26, 2011 3 comments
Antenna problems have existed in the chip manufacturing industry for more than one decade. In this paper,we present a systematic way to fix these problems.

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Categories: 6.ISSUES

Crosstalk – Overview and Modes

April 27, 2010 Leave a comment
  • What is Crosstalk?
  • Crosstalk Induced Noise
  • Effect of crosstalk on transmission line parameters
  • Crosstalk Trends Design Guidelines and Rules of Thumb

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Categories: 6.ISSUES

Leakage Reduction

April 17, 2010 Leave a comment

Semiconductor devices are aggressively scaled each technology generation to achieve high integration density while the supply voltage is scaled to achieve lower switching energy per device. To achieve high performance, however, commensurate scaling of the transistor threshold voltage …

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Categories: 6.ISSUES

Signal Integrity

April 16, 2010 2 comments

In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this book. In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced …

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Categories: 6.ISSUES

Clock Issues in Deep Submicron Design

April 16, 2010 Leave a comment
  • The Issues of Clock Tree Synthesis
  • The Basic Consideration of Clock Tree Synthesis
  • Traditional Clock Routing Algorithm
  • Recent Approaches in Clock Tree Synthesis

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Categories: 6.ISSUES