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Archive for the ‘5.LAYOUT’ Category

Transistors, Fabrication, Layout

April 11, 2013 Leave a comment

 

Look at the behavior of crystalline silicon

  • At temperatures close to 0 K, electrons in outermost shell tightly bound (insulator)
  • At higher temps., (300 K), some electrons have thermal energy to break covalent bonds

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Categories: 5.LAYOUT

Layout of Analog Circuits

April 3, 2013 Leave a comment

Issues of Analog Layout

  • Use of more number vias
  • Fingering and proper orientation
  • Device matching
  • Symmetrical and common centriod layout design
  • Use of Guard ring and substrate trapping

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Categories: 5.LAYOUT

Lecture 5: Layout Techniques

March 27, 2013 Leave a comment

Agenda

  • MOS Fabrication Sequence
  • CMOS Design Rules
  • Layout Techniques
  • Layout Examples

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Categories: 5.LAYOUT

MOS Device Layout Techniques

March 27, 2013 Leave a comment

Table of Contents

  • Process Design Rules
  • Layout of Resistors
  • Layout of Capacitors
  • Layout of MOS Transistors
  • References

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Categories: 5.LAYOUT

Matching in Analog Integrated Circuits

March 27, 2013 Leave a comment

In Analog Design Ratios are more important than the Absolute Value

  • Absolute values depend on large parameter drifts.Ratios depend on local variation of parameters
  • Specs of Analog/RF Circuits rely critically on Ratios
  • Cap/Res
  • MOS

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Categories: 5.LAYOUT

Analog layout design

March 19, 2013 Leave a comment

Layers

Legend of layers

  • Layer numbers are assigned to Well, Active, Poly, Contact, Metal, Via, Silicide Protect, and Dummy, respectively.
  • Some layer is automatically generated from the pattern on the drawn layer.
Categories: 5.LAYOUT

Layout of Analog CMOS – part 3

June 7, 2010 Leave a comment

Outline

  • Introduction
  • Process and Overview Topics
  • Transistors and Basic Cells Layout
  • Passive components: Resistors, Capacitors
  • System level Mixed-signal Layout

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Categories: 5.LAYOUT