Archive for the ‘ASIC’ Category

ASIC Physical Design Post-Layout Verification

January 29, 2014 Leave a comment


ASIC Physical Design (Standard Cell)

Mentor Graphics Analog/Mixed-Signal IC Design Flow


Calibre Layout-vs-Schematic (LVS) Check

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Categories: 2.DIGITAL, ASIC


May 27, 2010 Leave a comment

(Application Specific Integrated Circuit) Pronounced “a-sick.” A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. The use of ASICs improve performance over general-purpose CPUs, because ASICs are “hardwired” to do a specific job and do not incur the overhead of fetching and interpreting stored instructions. However, a standard cell ASIC may include one or more microprocessor cores and embedded software, in which case, it may be referred to as a “system on a chip” (SoC).

     A full custom ASIC chip is the most costly, and like standard cell ASICs, use a custom-designed mask for every layer in the chip. Unlike standard cells, designers of a full custom device have total control over the size of every transistor forming every logic gate, so they can “fine tune” each gate for optimum performance. Thus, a full custom ASIC performs electronic operations as fast as it is possible to do so, providing that the circuit design is efficiently architected.

     Today, full custom ASICs represent a small percentage of the ASIC market because gate arrays, structured ASICs and standard cells turn circuit designs into working chips much faster and at much less cost. Such chips have greatly improved in speed over the years and provide the necessary performance for many applications. The speed advantage of a full custom ASIC is not as relevant as it was in the past. It is used primarily for devices such as microprocessors that must run as fast as possible and will be produced in huge quantities.

Categories: 2.DIGITAL, ASIC

Asic Design – flowchart

April 20, 2010 Leave a comment

Show you the early stage all the way until the final stage with the recommended software of each stage.

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Categories: 2.DIGITAL, ASIC

ASIC Design Flow

March 17, 2010 Leave a comment

Step 1: Prepare an Requirement Specification

Step 2: Create an Micro-Architecture Document.

Step 3: RTL Design & Development of IP’s

Step 4: Functional verification all the IP’s/Check whether the RTL is free from Linting Errors/Analyze whether the RTL is Synthesis friendly.

Step 4a: Perform Cycle-based verification(Functional) to verify the protocol behaviour of the RTL Read more…

Categories: 2.DIGITAL, ASIC