Archive for the ‘2.DIGITAL’ Category

Delay Calculation

April 22, 2016 Leave a comment

Screen Shot 2016-04-22 at 4.06.50 PM

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Categories: 2.DIGITAL, Others

ASIC Physical Design Post-Layout Verification

January 29, 2014 Leave a comment


ASIC Physical Design (Standard Cell)

Mentor Graphics Analog/Mixed-Signal IC Design Flow


Calibre Layout-vs-Schematic (LVS) Check

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Categories: 2.DIGITAL, ASIC

Impact of Range and Precision on Standard Cell Libraries

May 30, 2013 Leave a comment


  1. Prior Approaches to finding the impact of the standard cell library
  2. Expressions to estimate suboptimality – Gate Sizes
  3. Experimental validation

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Categories: 2.DIGITAL, Standard Cell

Universal Gates

June 3, 2010 Leave a comment

In addition to AND, OR, and NOT gates, other logic gates like NAND and NOR are also used in the design of digital circuits.
The NOT circuit inverts the logic sense of a binary signal.
The small circle (bubble) at the output of the graphic symbol of a NOT gate is formally called a negation indicator and designates the logical complement…

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Categories: 2.DIGITAL


May 27, 2010 Leave a comment

(Application Specific Integrated Circuit) Pronounced “a-sick.” A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. The use of ASICs improve performance over general-purpose CPUs, because ASICs are “hardwired” to do a specific job and do not incur the overhead of fetching and interpreting stored instructions. However, a standard cell ASIC may include one or more microprocessor cores and embedded software, in which case, it may be referred to as a “system on a chip” (SoC).

     A full custom ASIC chip is the most costly, and like standard cell ASICs, use a custom-designed mask for every layer in the chip. Unlike standard cells, designers of a full custom device have total control over the size of every transistor forming every logic gate, so they can “fine tune” each gate for optimum performance. Thus, a full custom ASIC performs electronic operations as fast as it is possible to do so, providing that the circuit design is efficiently architected.

     Today, full custom ASICs represent a small percentage of the ASIC market because gate arrays, structured ASICs and standard cells turn circuit designs into working chips much faster and at much less cost. Such chips have greatly improved in speed over the years and provide the necessary performance for many applications. The speed advantage of a full custom ASIC is not as relevant as it was in the past. It is used primarily for devices such as microprocessors that must run as fast as possible and will be produced in huge quantities.

Categories: 2.DIGITAL, ASIC

Verilog Tutorial

April 25, 2010 Leave a comment

Verilog tutorial by :

Dr. D. K. Blandford

Department of Electrical Engineering and Computer Science

University of Evansville

February 23, 2006

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Categories: 2.DIGITAL, Verilog

Asic Design – flowchart

April 20, 2010 Leave a comment

Show you the early stage all the way until the final stage with the recommended software of each stage.

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Categories: 2.DIGITAL, ASIC