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Delay-Locked Loops (DLLs)

March 20, 2013 Leave a comment
  • DLLs lock delay of a voltage-controlled delay line (VCDL)
  • Typically lock the delay to 1 or 1⁄2 input clock cycles
  • If locking to 1⁄2 clock cycle the DLL is sensitive to clock duty cycle
  • DLL does not self-generate the output clock, only delays the input clock

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Categories: 1.ANALOG, DLL

Delay-locked loops

March 14, 2013 Leave a comment

Introduction •

Delay-Locked Loops
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  • –  DLL overview
  • –  CMOS, refreshing your memory
  • –  Building blocks:

• VCDL • PD
• LF

  • –  DLL analysis: • Linear

    • Nonlinear

  • –  Lock acquisition
  • –  Charge sharing
  • DLL Applications
  • Phase-Locked Loops
  • PLL Applications

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Categories: 1.ANALOG, DLL