Home > 1.ANALOG, Readout Circuit > Design and tests of pixel readout circuits in 65 nm CMOS

Design and tests of pixel readout circuits in 65 nm CMOS

  • SVTs at the next generation colliders ask for highly pixellated detectors, with
    ◦ analog (amplification, filtering, discrimination and possibly even A/D conversion)◦ digital (data sparsification, time stamping and buffering) functions integrated in the pixel itself
  • Designers are currently considering two different approaches: ◦ moving to higher density 2D technology nodes◦ moving to 3D technologies with vertical integration techniques
  • Standard 2D technologies: the 130 nm and 90 nm CMOS nodes are currently the focusof integrated circuit designers for the project of ASICs in future detector applications
  • The 65 nm process is starting to be considered as a new attractive solution in view of the development of high-density, high-performance mixed-signal readout circuits
  • Below 100 nm minimum feature size, the choice of the best technology to be used in ASIC design is a tricky problem, since transistor performance changes as CMOS technologies are scaled down into the nanoscale regime
  • The impact of new dielectric materials and processing techniques (silicon strain, gate oxide nitridation) on the analog behavior of MOSFETs has to be carefully evaluated

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Categories: 1.ANALOG, Readout Circuit
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