Advertisements
Home > Synopsys > Verilog Synthesis

Verilog Synthesis

SYNTHESIS is the process of taking a behavioral Verilog file and convertingit to a structural file using cells from a standard cell library.That is, the behavior that is captured by the Verilog program is synthesized into a circuit that behaves in the same way. The synthesized circuit is described as a collection of cells from the target cell library. This Verilogfile is known as structural because it is strictly structural instantiations of cells. It is the Verilog text equivalent of a schematic. This structural file can be used as the starting point for the backend tools which will place those cells on the chip and route the wire connections between them…

Read more

Advertisements
Categories: Synopsys
  1. No comments yet.
  1. No trackbacks yet.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: