Verilog Synthesis

SYNTHESIS is the process of taking a behavioral Verilog file and convertingit to a structural file using cells from a standard cell library.That is, the behavior that is captured by the Verilog program is synthesized into a circuit that behaves in the same way. The synthesized circuit is described as a collection of cells from the target cell library. This Verilogfile is known as structural because it is strictly structural instantiations of cells. It is the Verilog text equivalent of a schematic. This structural file can be used as the starting point for the backend tools which will place those cells on the chip and route the wire connections between them…

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