Antenna problems have existed in the chip manufacturing industry for more than one decade. In this paper,we present a systematic way to fix these problems.
Semiconductor devices are aggressively scaled each technology generation to achieve high integration density while the supply voltage is scaled to achieve lower switching energy per device. To achieve high performance, however, commensurate scaling of the transistor threshold voltage …
In the realm of high-speed digital design, signal integrity has become a critical issue, and is posing increasing challenges to the design engineers. Many signal integrity problems are electromagnetic phenomena in nature and hence related to the EMI/EMC discussions in the previous sections of this book. In this chapter, we will discuss what the typical signal integrity problems are, where they come from, why it is important to understand them and how we can analyze and solve these issues. Several software tools available at present for signal integrity analysis and current trends in this area will also be introduced …
In oxide chemical-mechanical polishing (CMP) processes, variations in dielectric thickness can reduce yield and affect performance. Metal fill patterns are commonly used to reduce layout dependent thickness variation, but they become more important especially at 130 nm and below. Metal-fill patterning can be performed in First Encounter. It fills large open areas on each metal layer with a metal pattern, which is either grounded or left floating, to compensate for pattern-driven variations. Fill metal algorithms add metal to achieve a certain metal density per “window” area, since dielectric thickness variation is proportional to fill pattern density. Put another way, if through fill metal you reduce the range in pattern density by 50%, then the resulting dielectric thickness variation should be reduced by half as well. The goal of metal-fill patterning is to meet the dielectric thickness variation spec for your foundry’s lithography requirements, while minimizing added interconnect capacitance. This paper will examine how fill metal affects parasitics, and whether grounded fill has any advantage over floating fill, if all else is held equal…
